The present disclosure relates generally to integrated circuit design, and more particularly to methods and computer program products for improving shape processing and reducing analysis time of via capacitance extraction.
As very large scale integrated circuit (VLSI) chips have increased size and complexity over the decades, interconnect width and spacing has also scaled. If the VLSI chip is not properly designed, the performance of the IC chip designed may be limited because of certain parasitic characteristics of the IC chip, and interactions between the components and conducting wires that are so close in space. Crosstalk can also limit the performance and function of the IC chip. Therefore, the effects of the interactions and crosstalk cannot be ignored, and must be accurately estimated.
In electronic design automation (or EDA), parasitic extraction is performed in order to “extract” electrical characteristics of a physical layout of an integrated circuit (IC). Parasitic extraction is calculation of the parasitic effects in both the designed devices and the required wiring interconnects (also generally referred to as “nets”) of the IC. The common electrical characteristics that are extracted from the physical layout of the IC include capacitance and resistance in the electronic devices within the IC and on the various nets that electrically connect the aforementioned electronic devices. These capacitance and resistance values are not intended by the designer but rather result from the underlying device physics of the device configurations and materials used to fabricate the IC. These unintended capacitance and resistance values may cause the performance of the IC to deteriorate. Therefore, an accurate estimation of the parasitic elements composing the nets is crucial for understanding the performance of the ICs, and to create an accurate analog model of the circuit before they are manufactured, so that detailed simulations can emulate actual digital and analog circuit responses and ascertain that the extra extracted parasitics will still allow the designed IC to function properly as designed.
An extractor tool is used to perform the parasitic extraction. The parasitic capacitance is calculated by giving the extraction tool the top view layout of the design in the form of input polygons on a set of layers; a mapping to a set of devices and pins (from a Layout Versus Schematic run), and a cross sectional understanding of these layers. This information is used to create a set of layout wires that have added capacitors where the input polygons and cross sectional structure indicate. The extraction tool acts on global nets, the set of shapes that constitute the chip's cell to cell connections. Global nets will have very large number of nets and shapes making up the nets, making it very difficult to hold all in memory, and is often very compute-intensive to analyze. For example, an extraction of a large flat core can take many hours, sometime, more than 12 hours. It is desirable to have a processing method to extract the parasitic capacitance without sacrificing the accuracy.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.